The present invention relates to a technique for generating a reference voltage of a semiconductor integrated circuit and, more particularly, to a band gap type reference voltage generating circuit which operates on a low power supply voltage. The invention relates to a technique effectively applied to a reference voltage generating circuit for generating a reference voltage necessary for, for example, an A/D converter or a D/A converter.
Since a reference voltage is necessary for a converting operation in an A/D converter or a D/A converter, a semiconductor integrated circuit having therein an A/D converter or a D/A converter is provided with a reference voltage generating circuit. Reference voltage generating circuits in various circuit forms using a zener diode, a differential amplifier, and the like are known. Among the circuits, a circuit called a band gap reference circuit can generate a stable reference voltage having low power supply voltage dependency and low temperature dependency. Consequently, the band gap reference circuit is often used in an analog circuit such as an A/D converter, a D/A converter, or the like and a circuit including analog and digital elements required to have high precision.
On the other hand, in recent years, the power supply voltage is being lowered for lower power consumption and higher processing speed in a semiconductor integrated circuit. Accordingly, a reference voltage generating circuit provided in the semiconductor integrated circuit, that can generate a lower reference voltage is being developed.
As an example of an invention related to a reference voltage generating circuit for generating a lower reference voltage, there is a reference voltage generating circuit disclosed in Japanese Patent Laid-open No. 2004-206633. FIG. 9 shows an example of a reference voltage generating circuit disclosed in Japanese Patent Laid-open No. 2004-206633. In the reference voltage generating circuit, output voltage (Vc) of a differential amplifier AMP0 is applied to the gate terminals of MOS (Metal Oxide Semiconductor) transistors MT1, MT2, and MT0. Consequently, if the sizes of the transistors are the same, currents I0 of the same magnitude flow.
In the reference voltage generating circuit, the drain voltage of the transistors MT1 and MT2 is applied to a pair of differential input terminals of a differential amplifier AMP0. By imaginary short action of the differential amplifier AMP0, feedback is performed so that the difference between inputs Vc1 and Vc2 becomes zero. Consequently, a voltage equal to the difference between a base-emitter voltage VBE1 of a bipolar transistor BT1 and a base-emitter voltage VBE2 of a bipolar transistor BT2 is generated in a resistor R1. The drain current I0 of the transistors MT1 and MT2 is determined so as to maintain this state.
The current I0 is copied by the transistor MT0 forming a current mirror in cooperation with the transistors MT1 and MT2 and passed to an output circuit including a resistor Ra, a diode-connected transistor BT3, and a resistor Rb connected in parallel with the resistor Ra and the transistor BT3, thereby enabling low voltage output to be obtained. Since a base-emitter voltage VBE0 of the transistor BT3 has a negative temperature characteristic such that the base-emitter voltage VBE0 decreases when the temperature rises, output voltage Vbgout corresponding to a voltage obtained by adding a voltage across terminals of the resistor Ra to VBE0 is compensated by the current I0 having a positive temperature characteristic flowing in the resistors Ra and Rb, and set to a desired voltage value having no temperature dependency.